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Espressif Systems /ESP32-S2 /I2S0 /CONF

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Interpret as CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TX_RESET)TX_RESET 0 (RX_RESET)RX_RESET 0 (TX_FIFO_RESET)TX_FIFO_RESET 0 (RX_FIFO_RESET)RX_FIFO_RESET 0 (TX_START)TX_START 0 (RX_START)RX_START 0 (TX_SLAVE_MOD)TX_SLAVE_MOD 0 (RX_SLAVE_MOD)RX_SLAVE_MOD 0 (TX_RIGHT_FIRST)TX_RIGHT_FIRST 0 (RX_RIGHT_FIRST)RX_RIGHT_FIRST 0 (TX_MSB_SHIFT)TX_MSB_SHIFT 0 (RX_MSB_SHIFT)RX_MSB_SHIFT 0 (TX_SHORT_SYNC)TX_SHORT_SYNC 0 (RX_SHORT_SYNC)RX_SHORT_SYNC 0 (TX_MONO)TX_MONO 0 (RX_MONO)RX_MONO 0 (TX_MSB_RIGHT)TX_MSB_RIGHT 0 (RX_MSB_RIGHT)RX_MSB_RIGHT 0 (TX_LSB_FIRST_DMA)TX_LSB_FIRST_DMA 0 (RX_LSB_FIRST_DMA)RX_LSB_FIRST_DMA 0 (SIG_LOOPBACK)SIG_LOOPBACK 0 (TX_FIFO_RESET_ST)TX_FIFO_RESET_ST 0 (RX_FIFO_RESET_ST)RX_FIFO_RESET_ST 0 (TX_RESET_ST)TX_RESET_ST 0 (TX_DMA_EQUAL)TX_DMA_EQUAL 0 (RX_DMA_EQUAL)RX_DMA_EQUAL 0 (PRE_REQ_EN)PRE_REQ_EN 0 (TX_BIG_ENDIAN)TX_BIG_ENDIAN 0 (RX_BIG_ENDIAN)RX_BIG_ENDIAN 0 (RX_RESET_ST)RX_RESET_ST

Description

I2S configuration register

Fields

TX_RESET

Set this bit to reset transmitter.
RX_RESET

Set this bit to reset receiver.
TX_FIFO_RESET

Set this bit to reset TX FIFO.
RX_FIFO_RESET

Set this bit to reset RX FIFO.
TX_START

Set this bit to start transmitting data.
RX_START

Set this bit to start receiving data.
TX_SLAVE_MOD

Set this bit to enable slave transmitter mode.
RX_SLAVE_MOD

Set this bit to enable slave receiver mode.
TX_RIGHT_FIRST

Set this bit to transmit right channel data first.
RX_RIGHT_FIRST

Set this bit to receive right channel data first.
TX_MSB_SHIFT

Set this bit to enable transmitter in Phillips standard mode.
RX_MSB_SHIFT

Set this bit to enable receiver in Phillips standard mode.
TX_SHORT_SYNC

Set this bit to enable transmitter in PCM standard mode.
RX_SHORT_SYNC

Set this bit to enable receiver in PCM standard mode.
TX_MONO

Set this bit to enable transmitter in mono mode.
RX_MONO

Set this bit to enable receiver in mono mode.
TX_MSB_RIGHT

Set this bit to place right channel data at the MSB in TX FIFO.
RX_MSB_RIGHT

Set this bit to place right channel data at the MSB in RX FIFO.
TX_LSB_FIRST_DMA

1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB transform from high bits.
RX_LSB_FIRST_DMA

1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB transform from high bits.
SIG_LOOPBACK

Enable signal loopback mode with transmitter module and receiver module sharing the same WS and BCK signals.
TX_FIFO_RESET_ST

I2S TX FIFO reset status. 1: I2S_TX_FIFO_RESET is not completed. 0: I2S_TX_FIFO_RESET is completed.
RX_FIFO_RESET_ST

I2S RX FIFO reset status. 1: I2S_RX_FIFO_RESET is not completed. 0: I2S_RX_FIFO_RESET is completed.
TX_RESET_ST

I2S TX reset status. 1: I2S_TX_RESET is not completed. 0: I2S_TX_RESET is completed.
TX_DMA_EQUAL

1: Data in left channel is equal to data in right channel. 0: Data in left channel is not equal to data in right channel.
RX_DMA_EQUAL

1: Data in left channel is equal to data in right channel. 0: Data in left channel is not equal to data in right channel.
PRE_REQ_EN

Set this bit to enable I2S to prepare data earlier.
TX_BIG_ENDIAN

I2S TX byte endianness.
RX_BIG_ENDIAN

I2S RX byte endianness.
RX_RESET_ST

I2S RX reset status. 1: I2S_RX_RESET is not completed. 0: I2S_RX_RESET is completed.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data